1. Technical Field
This invention generally relates to the testing of digital to analog converters, and more specifically relates to a test structure and method for testing digital to analog converters using on-chip components.
2. Background Art
A digital to analog converter, or DAC, is used wherever it is necessary to convert a digitally processed signal into a continuous output signal. As is clear from its name, a DAC accepts an input in digital form and converts it to the analog signal seen at the output of the DAC. During the manufacturing process a DAC is tested in various ways to ensure that its performance meets acceptable standards. The particular tests applied to a DAC are determined according to its target application and manufacturing cost considerations. Generally speaking, DACs targeted for higher performance applications can tolerate a higher manufacturing cost, and thus a more extensive testing process, because they have a higher selling price. Market pressures, however, are driving costs downward while elevating performance expectations, thus increasing the need for efficient and inexpensive testing methods.
There are two basic categories of DAC tests, namely static, or direct current (DC) tests, and dynamic, or alternating current (AC) tests. Dynamic testing requires specialized equipment and is usually reserved for high performance DACs. Static testing, on the other hand, can usually be accomplished without specialized tester resources and can be done instead using a test resource known as a parametric measurement unit (PMU) that is available on virtually any manufacturing test system. A DAC""s offset, gain, and linearity will conventionally be tested.
Offset is measured by conditioning the digital input of the DAC with a signal, such as an input code, intended to result in a minimum analog output voltage. The word code herein also includes a signal of any kind that may be input to a device. A tester PMU is then used to measure the analog output which is then compared, via the test program software, to a predefined pass/fail limit, sometimes referred to as the zero code. The parameter measured by the test program software is sometimes referred to as zero code error (ZCE). Gain is measured in a similar manner. The digital input is conditioned with a signal, such as a code, intended to result in a maximum analog output voltage. The PMU is used to measure the actual analog output. The test program then processes the result to obtain the gain.
Linearity tests are based on the assumption that each DAC input code results in a unique analog output. The conversion function is such that increasing values of input code result in linearly increasing values of output code. Although not every DAC design fits this pattern, the vast majority manufactured today do fall into this category. The most frequently applied linearity tests are for differential non-linearity (DNL) and integral non-linearity (INL).
DNL can be understood as the difference between the ideal and the actual analog step size between successive binary input codes. For example, if a binary input code of 01 ideally results in an analog output of 1.0 and a binary input code of 10 ideally results in an analog output code of 2.0, then the ideal step size is 1.0 (i.e., 2.0xe2x88x921.0). The DNL test at this code consists of measuring the actual analog outputs resulting from these two binary input codes and subtracting them. Ideally, the difference should be 1.0. If the difference is 1.2, then the DNL error is 0.2. In practice, this value is compared to a predefined pass/fail limit by the test program software.
INL can be understood as the worst case deviation from a linear response. This parameter is evaluated across all of the possible digital input to analog output combinations. There are a number of ways to test this in manufacturing. The data acquisition method is conventionally the same as that used for DNL. The main difference between the two is the calculations made by the test program after the data are collected. In real world practice, DNL and INL calculations are often based on a subset of all possible conversion values, to save manufacturing costs.
A current methodology for performing the various DAC tests described above is based on the design of a Video DAC (VDAC) core, which allows placing the circuit into a special test mode where the VDAC generates its own digital input pattern. This pattern is incremented by a digital clock supplied by the test system. The measurement technique is the same as described above. The analog outputs of the VDAC are measured using the tester PMU.
A VDAC is constructed as a bank of current switches. In operation, the output current is derived by summing a number of individual current sources into a single output node. The individual current sources are designed to have different output values. The actual values are multiples of something known as the Least Significant Bit (LSB). This is the finest resolution the converter can achieve. The current sources have values of 1, 2, 4, and 8 LSBs. The actual value of current supplied by each current source is determined by a reference current generator built into the VDAC core design. The reference current is defined by the value of a resistor that is separate from the IC containing the VDAC. This resistor doesn""t exist in the standard IC test environment. To alleviate the need for custom test interface hardware that includes the resistor, the VDAC is designed to contain an internal resistor that is used only during testing to supply the required current source reference during manufacturing test. This resistor is sensitive to manufacturing process variations.
The test procedure described above accomplishes manufacturing test goals by verifying that all of the VDAC current sources are operational, dynamically accounting for process variations in the xe2x80x9ctest onlyxe2x80x9d reference resistor. The test also verifies DC gain and offset accuracy, and provides an effective screen against non-linearities associated with manufacturing process defects.
The current testing methodology described in the foregoing paragraphs requires a separate test resource such as a PMU to make the needed measurements. This requirement leads to several drawbacks in and complications of the testing process. The most obvious of these may be the fact that a test resource embodied in a separate piece of equipment must first be located and then physically brought to the test site and coupled to the device being tested. Further, testing with an external resource is relatively slow and inefficient, and limits the types of tests that may be performed.
Therefore, there existed a need to provide a DAC manufacturing test resource that overcomes the problems of the current solutions by increasing the speed and accuracy with which a manufacturing test may be performed, increasing the available types of tests that may be run, and providing access to internal nodes that are not accessible to an external tester resource. According to the present invention, a DAC is part of an integrated circuit (IC) that includes digital logic. The digital logic includes the combinational and sequential control required to facilitate Built In Self Test (BIST) of the type previously employed in other solutions. The digital logic is presumed to drive the input of the DAC, which consists of a number of digital signals. These inputs are translated, as a function of the DAC design, into an analog output. During manufacturing test, this analog output is measured in order to determine that the IC has been manufactured correctly.
The circuitry of the present invention is connected between the DAC output and the digital logic on the IC. The analog input of the test circuitry is coupled to the analog output of the DAC. The two digital outputs of the test circuitry are coupled to the digital logic on the IC. This configuration comprises a BIST structure. The invention allows a BIST by eliminating the need to measure the analog output of the DAC external to the IC.
The circuit of the present invention is connected between the DAC and the digital logic on an IC, and may comprise a sample and hold (S/H) circuit, a sample and hold (S/H) clock, a latch clock, and two comparators with differing internal offsets, with the offsets selected based primarily on the DNL specification for the DAC. In one embodiment of the invention, the offsets are different multiples of the difference between a predicted output voltage of the DAC at a first time T1 and at a second time T2. The predicted output signals or voltages may differ from the actual output voltages produced when an input of the DAC is stimulated with a code intended to produce the predicted output voltage. The words signal, voltage, and code are used interchangeably herein.
In one embodiment of the invention, the testing method comprises the steps of: (1) sampling and holding a first actual output signal or voltage of the microelectronic device being tested, where the first actual output signal is representative of an output of said microelectronic device at a first time T1; (2) stimulating the device being tested causing the actual output signal or voltage of the microelectronic device to be updated to a second actual output signal representative of an output of said microelectronic device at a second time T2; (3) comparing the first and second output signals; and (4) returning a status signal indicative of the performance of the microelectronic device.
In a particular embodiment of the invention, a manufacturing test is performed by running a series of test cycles wherein each test cycle includes the following steps: The number of test cycles included in a test is arbitrary, and may vary from one manufacturing test to another. The first step in each test cycle conventionally involves stimulating the inputs of a DAC with a code intended to produce a predicted output signal. The DAC actual output signal is then sent to the comparators described herein, which compare the first actual output signal with the second actual output signal. The comparators contain a fixed internal offset, as will be further described in connection with FIG. 4, and return a signal indicative of the performance of the DAC. The digital outputs of the comparators are sampled using standard digital latches.
Because the circuit of the present invention is entirely contained on the IC, there is no need for a PMU or any other tester resource to make the measurements. This allows the test to run significantly faster, reducing manufacturing test costs. Faster testing also allows testing more codes, which may improve test quality, and provides intrinsic AC test coverage: if the DAC doesn""t respond fast enough then it will fail the test. The on-chip location of the present invention further provides access to internal IC nodes that are not available at the IO pins. In addition, both low and high limits are set simultaneously rather than separately as in some previous solutions, thus saving time and expense. Front End Hardware (FEH) noise issues are also minimized or eliminated.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of specific embodiments of the invention, as illustrated in the accompanying drawings.